Engineering & computing · OECD FoS 2.2 · China MoE 1401 集成电路科学与工程
Electronics & chip design
电子与芯片设计
L2Local breakthroughs ↑ Rising Score 1.90 · Last reviewed 2026-10-21 · Next review 2027-01-19
BIGGEST BREAKTHROUGH 2026-08-26 AI · majorField · major
Architect Labs Redwood: AI accelerator designed, verified and FPGA-deployed by AI in two weeks ↗
All RTL/verification/firmware AI-generated; not yet taped out
Why this level
RL chip placement (AlphaChip) was used for several TPU generations (Nature 2021) but its reproducibility is disputed (CACM re-evaluation); in 2026 Synopsys pushes agentic EDA, with AMD reporting 25–40% shorter debug cycles (vendor figures).
S = 0.30·method + 0.35·discovery + 0.25·adoption + 0.10·education (education scores 0 when there is no evidence; if empty, the other weights are renormalised)
Sources
- nature.com/articles/s41586-021-03544-w
- doi.org/10.1145/3676845
- news.synopsys.com/2026-07-27-Synopsys-Advances-Agentic-AI-Chip-Design-with-AMD-and-Microsoft
Composite 1.5–2.49: at least one peer-reviewed/officially verified AI-key result, or one dimension at 3; routine workflow largely unchanged. All levels →
Research directions
Placement & routingVerification/debug agentsRTL generation
Papers
- Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI
All RTL/verification/firmware AI-generated; not yet taped out
2026-08-26 · arXiv
- Reevaluating Google’s Reinforcement Learning for IC Macro Placement
Independent re-evaluation challenging the original
2024-10-25 · Communications of the ACM
- ChipNeMo: Domain-Adapted LLMs for Chip Design
First systematic in-house LLM use for chip design
2023-10-31 · arXiv
- A graph placement methodology for fast chip design
RL floorplanning used in TPUs; reproducibility disputed
2021-06-09 · Nature
- HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference
Runs prefill on GPUs and decode on NPUs with heterogeneity-aware KV-cache transfer for efficient disaggregated inference.
2026-10-21 · arXiv · Junhyeok Park, Jungeun Yoon, Kyungmin Kim, Hunsoon Lee
- Hard and Soft Real-Time DNN Inference Scheduling on Heterogeneous Multi-Accelerator Systems via Reinforcement Learning
An online RL scheduler with a deterministic safety layer schedules hard and soft real-time DNN inference on heterogeneous accelerators.
2026-10-21 · arXiv · Francesco Giulio Blanco, Enrico Russo, Giuseppe Ascia, Davide Patti
- E-Layout: Layout-Stage Logic Restructuring via RL-Optimized Equality-Saturated Graph Retrieval-Augmented Generation
Layout-stage logic restructuring via RL-optimised equality-saturation graph RAG.
2026-10-19 · arXiv · Wenji Fang, Rongjian Liang, Yi-Chen Lu, Cunxi Yu
- A Hybrid GPU and Processing-Near-Memory Architecture with Shared DRAM for Efficient Prefill-Decode Disaggregation
A hybrid GPU + processing-near-memory architecture with shared DRAM for prefill–decode disaggregation.
2026-10-19 · arXiv · Sanghyeok Han, Inseong Choi, Byungkuk Yoon, Gyeonghwan Park
- Superposed analog memory for vector storage in neural networks
Analog memory storing multiple vectors in superposition in one array, recovered by in-memory MVM.
2026-10-19 · arXiv · Athanasios Vasilopoulos, Patrick Diener, Michael Hersche, Abbas Rahimi
- MX-Like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration
Joint HW–SW exploration of MX-like block-scaled formats for edge NPU LLM inference.
2026-10-19 · arXiv · Zijun Zhao, Ruichu Ao, Stef Cuyckens, Marian Verhelst
- 3D-MoE: Complementarity-Guided Hardware-Software Co-Design for MoE Decode on 3D-Stacked NMP
Hardware–software co-design exploiting expert complementarity to balance MoE decode on 3D-stacked near-memory processing.
2026-10-19 · arXiv · Yudong Pan, Lian Liu, Shixin Zhao, Yintao He
- Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation
For LLM RTL generation of SECDED wrappers, output representation matters more than the training regime.
2026-10-19 · arXiv · Siddharth Patel, Vikram Singh, Siddharth Savyasachi Malu, Rohit Singh
- From arXiv, bioRxiv, medRxiv and OpenAlex (last ~30 days); summaries written by AIMap from the abstract.
Milestones 8
Big glowing nodes are leaps: AI leap cool · Field leap warm · double ring = both
-
Benchmark
ChipAgents & NVIDIA launch Build-A-Chip-Bench for end-to-end autonomous chip designAI: covers RTL through signoff; Field: early agents pass functional verification ~40% but meet PPA targets only ~10%
ChipAgentsVendor claim -
System
Architect Labs Redwood: AI accelerator designed, verified and FPGA-deployed by AI in two weeksAll RTL/verification/firmware AI-generated; not yet taped out
arXivVendor claimPreprint -
Industry
Synopsys advances agentic AI chip design with AMD & MicrosoftVendor agentic EDA push
SynopsysVendor claim -
System
Verkor Design Conductor builds a RISC-V CPU from a 219-word spec to GDSII in 12 hours (simulation only)First spec-to-GDSII CPU by an agent; no silicon
Tom’s HardwareVendor claim -
Paper
Reevaluating Google's RL for IC macro placement (CACM)Independent re-evaluation challenging the original
Communications of the ACM -
Paper
ChipNeMo: domain-adapted LLMs for chip design (NVIDIA)First systematic in-house LLM use for chip design
arXivPreprint -
Paper
RL chip floorplanning (Nature)RL floorplanning used in TPUs; reproducibility disputed
NatureContested
No milestones match this filter.
More papers & repos 5
| Type | Title | Date |
|---|---|---|
| Paper | Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI Preprint | 2026-08-26 |
| Paper | Reevaluating Google’s Reinforcement Learning for IC Macro Placement | 2024-10-25 |
| Paper | ChipNeMo: Domain-Adapted LLMs for Chip Design Preprint | 2023-10-31 |
| Paper | A graph placement methodology for fast chip design | 2021-06-09 |
| Repo | google-research/circuit_training To be verified | — |
Latest news 7
- A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame)Semiconductor Engineeringen
- Vinci targets faster chip design and simulation with physics-driven AISiliconANGLE AIen
- OpenAI and Synopsys partner to build "GPT-Synopsys" for autonomous chip designTom's Hardware AIen
- AI chip designIEEE Spectrumen