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// Stage 6 · Inference, Deployment & Efficiency

GPUs, Distributed Training & AI Chips

Memory, bandwidth and compute; mixed precision; data/tensor/pipeline parallelism; ZeRO/FSDP; the chip landscape.

about 10 hours6 algorithms4 paperslesson text in progress

01Goals

Do these first: Pretraining, Data & Scaling Laws

02Algorithms to master

Each card has the original paper, prerequisites and resources.

03Must-read papers

04Courses & videos

05Hands-on: project, code & exercises

Free, official or author-published pages. Most run in the browser or on a free Colab GPU.

PROJECT

Train a small model with FSDP on 2 GPUs (or simulated on Colab) and compare memory use with DDP.

  1. 1
    srush/GPU-Puzzles ↗Exercises

    Solve 14 CUDA puzzles in a notebook to grasp threads, blocks and shared memory.

  2. 2
    triton-lang.org ↗Official docs

    Write Triton kernels for vector add, softmax and matmul with the official tutorials.

  3. 3
    github.com ↗Reference code

    Run data and tensor parallelism on several GPUs and compare communication.

06Self-test

Answer in your head, then open to check.

Roughly how many bytes per parameter does mixed-precision AdamW training take?

About 16 bytes (weights, gradients, two moments and master weights).

Is tensor parallelism for across machines or within one?

Within a machine, over fast interconnect.

What does ZeRO-3 shard?

Parameters, gradients and optimiser states.

On these routes: Algorithm Researchers

Data updated: AI algorithms & curriculum(UTC+8)